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File size:5.37 GB
Time:2026-10-02
Hit count :2 Related :UdemyBuildComputerFromScratchBinaryAssembly2026-9
File list
9 - Writing & Running Real Programs/47. Counting the Fibonacci Sequence on Our Computer.mp4-450.32 MB
6 - RAM, ROM & the Bus/25. Building RAM From Logic Gates & Connecting RAM and the ALU.mp4-369.81 MB
8 - The Control Unit/43. In-Detail Timing of Each CPU Instruction.mp4-364.44 MB
6 - RAM, ROM & the Bus/27. Introducing the BUS.mp4-281.27 MB
9 - Writing & Running Real Programs/46. Executing Our First Program.mp4-260.3 MB
6 - RAM, ROM & the Bus/28. Adding a Display to Our Computer (7-Segment Display).mp4-221.72 MB
4 - Building an ALU (Adders)/17. Enabling Subtraction in Our Circuit.mp4-208.99 MB
8 - The Control Unit/42. Implementing Control as ROM.mp4-194.39 MB
10 - From Breadboard to Real-World CPUs/48. Physically Constructing Our Conceptual Computer.mp4-188.91 MB
10 - From Breadboard to Real-World CPUs/50. The Original iPhone Processor.mp4-183.54 MB
6 - RAM, ROM & the Bus/30. Making Our Display Stateful.mp4-178.75 MB
6 - RAM, ROM & the Bus/24. Random Access Memory (RAM).mp4-153.47 MB
5 - Sequential Logic & Memory Storage/19. Storing Data With Logic Gates (Latches).mp4-153.14 MB
7 - Instructions & the Instruction Set Architecture/34. Building the First Instruction for Our CPU.mp4-137.22 MB
8 - The Control Unit/44. How Condition Instructions Are Implemented.mp4-134.65 MB
10 - From Breadboard to Real-World CPUs/51. ARMv6 Overview.mp4-125.92 MB
7 - Instructions & the Instruction Set Architecture/40. Adding a Flags Register to the ALU.mp4-115.77 MB
6 - RAM, ROM & the Bus/29. Read-Only Memory (ROM).mp4-115.29 MB
5 - Sequential Logic & Memory Storage/20. Introducing the Flip-Flop, a Better Latch.mp4-103.73 MB
7 - Instructions & the Instruction Set Architecture/35. Synchronizing the Computer Introducing the Clock.mp4-90.48 MB
5 - Sequential Logic & Memory Storage/22. Saving the Output of Our ALU.mp4-89.18 MB
9 - Writing & Running Real Programs/45. Writing Our First Computer Program!.mp4-82.04 MB
7 - Instructions & the Instruction Set Architecture/38. Designing the Instruction Set Architecture (ISA).mp4-79.3 MB
7 - Instructions & the Instruction Set Architecture/36. Program Counter.mp4-78.95 MB
10 - From Breadboard to Real-World CPUs/49. Naming and History of the Computer (SAP).mp4-77.55 MB
5 - Sequential Logic & Memory Storage/23. Building a Circuit That Counts Numbers.mp4-69.99 MB
2 - Number Systems & Binary Arithmetic/4. Converting from Decimal to Binary.mp4-68.51 MB
4 - Building an ALU (Adders)/14. Constructing a Full Adder.mp4-68.15 MB
4 - Building an ALU (Adders)/15. Chaining Adders Together for Multi-Bit Addition.mp4-64.23 MB
7 - Instructions & the Instruction Set Architecture/37. Clock Timing of Our First Instruction.mp4-62.67 MB
10 - From Breadboard to Real-World CPUs/53. How Does Our CPU Draw to a Screen (Intro to MMIO).mp4-61.4 MB
4 - Building an ALU (Adders)/16. Building a Full 8-Bit Addition Circuit (ALU).mp4-54.45 MB
2 - Number Systems & Binary Arithmetic/3. How Computers Represent Numbers (Intro to Binary).mp4-50.22 MB
2 - Number Systems & Binary Arithmetic/2. How Humans Represent Numbers (Decimal).mp4-48.68 MB
2 - Number Systems & Binary Arithmetic/6. Representing Negative Numbers in Binary.mp4-45.53 MB
3 - Logic Gates & Building Circuits/11. Building a Selector With Logic Gates.mp4-44.9 MB
8 - The Control Unit/41. Introducing Control, the Brains of Our Computer.mp4-43.81 MB
3 - Logic Gates & Building Circuits/9. Introduction to Logic Gates.mp4-43.19 MB
7 - Instructions & the Instruction Set Architecture/39. Branching in Code.mp4-39.33 MB
6 - RAM, ROM & the Bus/26. Connecting RAM and the ALU.mp4-35 MB
10 - From Breadboard to Real-World CPUs/52. Hexadecimal Mini-Course.mp4-34.92 MB
4 - Building an ALU (Adders)/12. Half-Adder Simple Binary Addition With Logic Gates.mp4-32.32 MB
2 - Number Systems & Binary Arithmetic/5. How Addition Works in Binary.mp4-31.82 MB
7 - Instructions & the Instruction Set Architecture/31. What Happens When We Start Chaining Operations.mp4-30.97 MB
7 - Instructions & the Instruction Set Architecture/33. The Instruction Register.mp4-21.6 MB
5 - Sequential Logic & Memory Storage/21. Bridging Back to the ALU.mp4-21.03 MB